In many electronic circuits, charge pump circuits are utilized to generate a positive pumped voltage having an amplitude greater than that of a positive supply voltage, or to generate a negative pumped voltage. For example, in a conventional dynamic random access memory (“DRAM”), a charge pump circuit may be utilized to generate a boosted word line voltage VCCP having an amplitude greater than the amplitude of a positive supply voltage VCC. A negative charge pump circuit may be utilized to generate a negative substrate or back-bias voltage VBB that may be applied to the bodies of NMOS transistors in a DRAM. Another typical application of a charge pump circuit may be the generation of a high voltage utilized to erase data stored in blocks of memory cells or to program data into memory cells in non-volatile electrically block-erasable or “FLASH” memories, as will be understood by those skilled in the art. Other electronic components besides memory devices also may make use of charge pump circuits.
An example of a conventional charge pump circuit 100 is shown in FIG. 1. An oscillating input signal, such as a clock signal, CLK, is applied to an input of an inverter 105. During a first phase of operation, when the CLK signal is high, node A is low, and node B is clamped to Vcc−Vth by the transistor 110. The voltage difference between Nodes A and B charges a capacitor 115. During a second phase of operation, the CLK signal transitions low, and Node A will transition high. As Node A rises to VCC, Node B will begin to rise above VCC−Vth, due to the charge stored in the capacitor 115. As the Node B voltage rises above VCC−Vth, the transistor 110 turns off, and transistor 120 turns on. Accordingly, the charge from the capacitor 115 is transferred through the transistor 120 and charges a load capacitor 125, raising the voltage VOUT. As the clock signal CLK continues to cycle, the load capacitor 125 continues to charge until the voltage at VOUT equals the peak voltage at Node B. Based on the charge pump circuit shown in FIG. 1, a simple negative voltage pump could be built by substituting PMOS transistors for the NMOS transistors 110 and 120 and moving their respective gate connections, as understood by those skilled in the art.
The simple charge pump circuit shown in FIG. 1 is a single-stage circuit, having only a single charging capacitor 115. The single-stage charge pump of FIG. 1 can generate at most a VCCP voltage equal to twice VCC, because the charge across charging capacitor 115 can be at most VCC, which stored voltage will be added to the original supply voltage VCC. Accordingly, to achieve still higher VCCP voltages, multiple stage charge pumps may be used. A conventional schematic for a stage 200 of a multi-stage charge pump is shown in FIG. 2.
The conventional stage 200 circuit includes inverter 205 and charging capacitor 215, analogous to the inverter 105 and charging capacitor 115 shown in FIG. 1. The transistors 110 and 120 from FIG. 1 are shown as idealized switches 210 and 220, respectively in FIG. 2. A clock signal, CLK, is applied to an input of the inverter 205. During a first, charging, phase, the switch 210 is closed, and a voltage is coupled from a previous stage (or from a source voltage in the case of the first stage) to the charging capacitor 215. During the second phase, as the CLK signal transitions, the switch 220 is closed and the charge stored on the charging capacitor 215 is coupled through to the next stage of the multi-stage charging circuit. Using multiple stages allows a larger voltage to be generated by the charge pump circuit.
Charge pump circuits are characterized in terms of capacity and efficiency—capacity referring to the amount of output current the charge pump supplies, and efficiency referring to either power efficiency (output power divided by input power) or current efficiency (output current divided by input current). The number of pump stages is related to the maximum current efficiency. Due to the charge pump stage architecture, the maximum current efficiency is given as 1/(K+1) where K is the number of pump stages. Accordingly, a pump having fewer stages will theoretically have greater maximum current efficiency. Conversely a pump having more stages will have a smaller maximum current efficiency, but will have a greater driving capacity for a given output voltage.